Design For Testability (DFT)

Enabling Testable, Reliable, and Production-Ready Silicon

Tenasic embeds testability early in the design process to achieve robust post-silicon testing, improved yield, and lower cost of production. Our tailored DFT methodologies align with each customer’s SoC design and high-volume manufacturing test requirements, ensuring thorough fault coverage and accelerated test cycles.

Full DFT Solution for High-Volume Manufacturing — Driving Quality, Efficiency, and Faster Time-to-Production

DFT & Test Methodology Solution

  • Scalable Test Access Architecture for Monolithic and 2.5D/2D SoC
  • High Fault Coverage ATPG Scan Methodology
  • Memory BIST Solution – Repairable & Non-Repairable Memory
  • JTAG Boundary Scan
  • Loopback BIST for high-speed IO
  • Analog IP Test Methodology
  • Manufacturing Trackability
  • Test Mode Security
  • On-chip Monitoring & Debug

SoC Product’s Experience

  • High Volume SoC with stringent DPPM & reliability requirements (Data Center & Industrial Control Application)
  • Low Volume, High Mixed 2.5D SoC products
  • Cost sensitive, high volume consumer SoC
  • Experience in handling fully abutted design and semi-custom IP DFT

End-to-End DFT Flow from Specification to Production Handoff with Robust Implementation and Sign-off Methodology

Pre-silicon Phase

  • DFT Architecture Spec
  • DFT Logic Integration (RTL & Netlist Handoff)
  • Formal Verification
  • RTL DFT DRC
  • Test Mode SDC & Timing Signoff
  • Scan Insertion
  • ATPG – Scan DRC, Test Coverage Analysis
  • IP Test Generation & Verification
  • RTL and Gate Level Simulation
  • DFT Tape-out Sign-off Process

Post-Silicon (NPI to Production) Phase

  • Test Patterns Handoff to ATE
  • ATE Test Bring-up Support
  • Diagnostic & Yield Improvement
  • Test Time Optimization