IP Solutions

Build Smarter, Faster, and Fully Custom SoCs with Our Proprietary IP Portfolio

At Tenasic, we offer a comprehensive IP portfolio designed in-house to accelerate SoC development across performance, efficiency, and scalability dimensions. Our silicon-proven IPs are the result of deep system-level understanding and real-world deployments—empowering our customers to reduce time-to-market while maintaining flexibility and control over design.

Whether you’re designing for AI at the edge, high-speed computing, or embedded control, our IPs are performance-validated and integration-ready, forming the backbone of successful SoC programs.

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CPU Cores

On-Chip Interconnect

System Components

High-Performance CPU Cores

Maximize compute. Minimize compromise.

Our RISC-V CPU cores deliver scalable performance for demanding workloads, including AI, edge computing, and data centers.

Key Features:

  • RV64GCBH architecture
  • 11+ stage out-of-order superscalar pipeline
  • 5-way decode/rename/commit
  • 32KiB/64KiB L1 instruction & data cache
  • Shared configurable L2 cache
  • Support for PLIC, CLINT
  • Multi-core cluster configurations (1/2/4 cores per cluster)
  • Dual FPU support (FP32/FP64, IEEE 754-2008)

Power-Efficient CPU Cores

Lean on power. Heavy on intelligence.

Our energy-efficient cores support RISC-V Vector Extensions (RVV) for AI acceleration, DSP, and edge inference—perfect for mobile, IoT, and embedded systems.

Key Features:

  • RV64GCBVH Architecture, supporting Vector 1.0, Vector Crypto Extensions
  • Pipeline stage: 10–15, out-of-order superscalar core
  • 3-way decode/rename/commit
  • 256-bit VLEN and DLEN, 2x128-bit Vector Execution Units
  • Broad Datatype Support: Integer INT8 to INT64, Floating Point BF16 / FP16 / FP32 / FP64
  • Shared configurable L2 cache
  • Multi-core cluster support
  • AIA and IOMMU compatibility

Coherent Network-on-Chip (NoC)

Unify your system. Accelerate your data.

Our NoC IP enables seamless, high-bandwidth communication between cores and peripherals, with full cache coherency.

Mesh Coherent NoC

  • Up to 144 nodes, 128 FCH nodes, 3–5 devices per node
  • Support for D2D and CXL interfaces
  • High throughput (512-bit channels), low latency
  • CHI protocol support, inclusive/non-inclusive LLC
  • IO coherence for PCIe, USB, SATA, etc.
  • QoS and concurrency support
  • Integrated RAS features (ECC, CRC, error reporting)
  • Power-saving techniques (partial cache power-down, clock gating)

Crossbar Coherent NoC

  • Scalability & Flexibility with support for multi-core / multi-cluster architectures
  • Component Aggregation Layer (CAL) for modular SoC integration and scalability
  • High IO & Memory Coherency with IO coherence for consistent memory access
  • QoS Features enabling IO transaction isolation via 2-way or 4-way cache partitioning
  • Advanced Cache Management (CMO) for software-triggered flush, invalidate, and clean operations
  • Low-Power Modes including cache way power-down, dynamic clock gating, and state retention
  • Reliability & Debug with ECC protection on Last-Level Cache (LLC) and enhanced post-silicon debugging
  • Optimized SoC Design balancing performance, reliability, and power, while simplifying bring-up and validation

System Infrastructure IPs

  • Security IPs – Secure boot, crypto acceleration, and zone enforcement
  • RAS IPs – ECC, diagnostics, and recovery for system-level robustness
  • Power Management IPs – Multi-domain DVFS, runtime monitoring, and power gating
  • Boot & Control IPs – Programmable FSMs for streamlined system bring-up
  • Debug IPs – Advanced trace, breakpoint, and observability features
  • IOMMU & Interrupt Controllers – Safe and predictable DMA and interrupt routing for both Arm® and RISC-V systems
  • USB-PD - Flexible Power Delivery Along With Data Over a Single cable